View NCP81042MNTXG_8284655.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2012 august, 2012 ? rev. p0 1 publication order number: ncp81042/d ncp81042 precise low voltage synchronous buck controller with power saving mode the ncp81042 is a simple single phase solution with differential phase current sensing, power saving operation, and gate drivers to provide accurately regulated power. the adaptive non overlap gate drive and power saving operation circuit provide a low switching loss and high efficiency solution for server, notebook, and desktop systems. a high performance operational error amplifier is provided to simplify compensation of the system. the ncp81042 features also include soft ? start sequence, accurate overvoltage and over current protection, uvlo for vcc and vccp, and thermal shutdown. features ? high performance operational error amplifier ? internal soft ? start/stop ? 0.5% internal voltage accuracy, 0.8 v voltage reference ? ocp accuracy, four re ? entry times before latch ? ?lossless? differential inductor current sensing ? internal high precision current sensing amplifier ? oscillator frequency range of 100 khz ? 1000 khz ? 20 ns adaptive fet non ? overlap time of internal gate driver ? 5.0 v to 12 v operation ? support 1.5 v to 19 v v in ? v out from 0.8 v to 3.3 v (5 v with 12 v cc ) ? chip enable through osc pin ? latched over voltage protection (ovp) ? internally fixed ocp threshold ? guaranteed startup into pre ? charged loads ? thermally compensated current monitoring ? thermal shutdown protection ? integrated mosfet drivers ? integrated boost diode with internal r bst = 2.2 ? automatic power saving mode to maximize efficiency during light load operation ? sync function ? remote ground sensing ? this is a pb ? free device* applications ? desktop and server systems *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com qfn16 case 485g marking diagrams 4 1 16 13 9 12 58 14 7 15 6 310 211 gnd ug pgood sync comp fb vsen fbg csn/vo boot lx lg vccp vcc rosc/en csp pin connections 1 81042 alyw 81042 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package (*note: microdot may be in either location) device package shipping ordering information NCP81042MNTXG qfn16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. (top view)
ncp81042 http://onsemi.com 2 figure 1. ncp81042 block diagram 4 5 3 1 2 16 13 12 8 9 boot ug lx vccp lg gnd csp csn/vo comp fb control logic, protection, ramp generator and pwm logic + ? + ? cdiff uvlo control ? + + ? vref*75% vref*125% uvp ovp osc error amplifier current sense amplifier + ? vref*50% ovp, unlatched 0.8v 11 10 vsen fbg 15 pgood 7 sync 14 rosc/en programmable osc vcc 6 1.24v 2.2 over current detector pin descriptions pin no. symbol description 1 vccp power supply for bottom gate mosfet drivers 2 lg bottom gate mosfet driver pin 3 lx switch node 4 boot supply rail for the floating top gate driver 5 ug top gate mosfet driver pin 6 pgood power good. it is an open ? drain output, set free after ss (with 3x clock delay) as long as the output voltage monitored through vsen is within specifications. 7 sync synchronization pin. the controller synchronizes on the falling edge of a square wave provided to this pin. short to gnd if not used. 8 comp output of the error amplifier 9 fb inverting input to the error amplifier 10 vsen output voltage sense 11 fbg remote ground sense 12 csn/vo inductor differential sense inverting input 13 csp inductor differential sense non ? inverting input 14 rosc/en programs the switching frequency; en: pull ? low to disable the device 15 vcc supply rail for the controller internal circuitry 16 gnd ground reference thermal pad connects with the silicon substrate for good thermal contact with the pcb. connect to gnd plane.
ncp81042 http://onsemi.com 3 rf1 jp3 etch 1 2 ch1 q3 3 1 2 rvfb1 rfb2 rsen1 rntc1 riso1 rfb3 cf1 enable vccp rs4 rosc1 vout csen1 cfb2 rs3 lout1 q4 3 1 2 vin cboot1 + cout1 vcc r2 r1 ncp81042 boot 4 comp 8 lg 2 lx 3 gnd 16 ug 5 vcc 15 csp 13 csn/vo 12 vccp 1 rosc/en 14 pgood 6 sync 7 fbg 11 fb 9 vsen 10 sync pgood figure 2. typical application circuit absolute maximum ratings rating symbol v max v min unit controller power supply voltages to gnd vcc, vccp 15 ? 0.3 v boost supply voltage input boot 35v wrt/gnd 40 v <100 ns wrt/gnd 15 wrt/lx ? 0.3 v high ? side driver output (top gate) ug 35 40 v 50 ns wrt/gnd 15 wrt/lx ? 0.3 wrt/lx ? 5 v < 200 ns v switching node (bootstrap supply return) lx 35 40 < 100 ns ? 5 ? 10 v < 200 ns v low ? side driver output (bottom gate) lg 15 ? 0.3 ? 5 v < 200 ns v all other pins 6 ? 0.3, ? 1 v < 1 s v pgood pgood 7 ? 0.3, ? 1 v < 1 s v sync sync 7 ? 0.3, ? 1 v < 1 s v current sense amplifier csp, csn/vo with v cc = 12 v 10 ? 0.3, ? 1 v < 1 s v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *all signals referenced to gnd unless noted otherwise.
ncp81042 http://onsemi.com 4 thermal information rating symbol typ unit thermal resistance, junction ? to ? ambient r ja 60 c/w thermal resistance, junction ? to ? case r jc 18 c/w operating junction temperature range t j 0 to 125 c operating ambient temperature range t a 0 to 85 c maximum storage temperature range t stg ? 55 to +150 c moisture sensitivity level qfn package msl 1 ? electrical characteristics unless otherwise stated: 0 c < t a < 85 c; 4.5 v < vcc < 13.2 v; c vcc = 0.1 f parameter test conditions min typ max unit supply operating conditions vcc voltage range 4.5 13.2 v vccp voltage range 4.5 13.2 v dv/dt on vcc (note 1) ? 10 10 v/ s dv/dt on vccp (note 1) ? 10 10 v/ s vcc and boot input supply current vcc operating current v cc = 5 v, en = high v cc = 12 v, en = high 5.0 ma vcc supply current v cc = 5 v, en = low v cc = 12 v, en = low 400 ua vccp input supply current vccp operating current ug and lg open v ccp = 5 v, en = high v ccp = 12 v, en = high 3.5 5.0 ma vccp supply current v ccp = 5 v, en = low v ccp = 12 v, en = low 200 a vcc supply voltage vcc uvlo start threshold v cc rising 4.50 v vcc uvlo hysteresis v cc rising or falling 300 mv vccp supply voltage vccp uvlo start threshold 4.2 v vccp uvlo hysteresis 200 mv error amplifier comp open loop dc gain (note 1) 120 db open loop unity gain bandwidth (note 1) 15 18 mhz slew rate (note 1) comp pin to gnd with 100 pf load 8.0 v/ s vref internal reference voltage 0.800 v output voltage accuracy v out to fbg excluding external resistor divider tolerance ? 0.5 0.5 % current sense amplifiers common mode input voltage range (note 1, gng, output within 10mv) v cc 7.5 v ? 0.3 3.5 v common mode input voltage range (note 1, gng, output within 10 mv) v cc > 7.5 v ? 0.3 5.5 v 1. guaranteed by design. 2. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram.
ncp81042 http://onsemi.com 5 electrical characteristics unless otherwise stated: 0 c < t a < 85 c; 4.5 v < vcc < 13.2 v; c vcc = 0.1 f parameter unit max typ min test conditions oscillator (with no rosc resistor defaults to 200 khz) switching frequency accuracy r osc open ? 10 10 % osc gain (note 1) 10 khz / a disable threshold r osc /en pin, v dis_th 0.75 v modulators (pwm comparators) minimum pulse width f sw = 200 khz, osc open 90 ns minimum turn off time (lg on) f sw = 200 khz, osc open 250 350 450 ns magnitude of the pwm ramp v in = 5 v or 12 v 1.50 v maximum duty cycle osc/en = open 80 95 % minimum skip mode frequency in light load, maximum time for lg to turn on after hg turns off 30 khz soft ? start soft start time @ 200 khz 1024 clock cycles, osc/en open 5.12 ms soft ? off soft off bleeding resistor r dis 120 over current protection first over current threshold csp ? csn, 4xmasking 17 20 23 mv second over current threshold csp ? csn, immediate action 30 mv sync pin synchronization input vil, square wave 1.0 v synchronization input vih, square wave 2.5 v protection and pgood output voltage logic low, sinking 4 ma 0.4 v ovp threshold vsen rising above 1.25 * v ref 117 125 130 % uvp threshold vsen falling below 0.75 * v ref 70 75 80 % unlatched overvoltage threshold v th_disoff with respect to 0.5 v ref 40 50 60 % power good high delay (note 1) 50 s power good low delay (note 1) 1 s zero current detection (lx pin) blanking time before zero current detection (note 1) blanking time after lg is < 1.0 v 40 ns capture time for lx voltage (note 1) time to capture lx voltage once lg is < 1.0 v (must be within dead time limits) 20 ns negative lx detection voltage v bdls 150 300 450 mv positive lx detection voltage v bdhs 0.2 0.5 1.0 v time for v th adjustment and settling time (note 1) 300 khz 3.0 3.7 s initial negative current detection threshold voltage set point (note 1) lx ? gnd, includes 2 mv offset range 1.0 mv v th adjustable range (note 1) ? 16 0 15 mv 1. guaranteed by design. 2. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram.
ncp81042 http://onsemi.com 6 electrical characteristics unless otherwise stated: 0 c < t a < 85 c; 4.5 v < vcc < 13.2 v; c vcc = 0.1 f parameter unit max typ min test conditions high side driver ug r h_tg output resistance, sourcing v boot ? v lx = 12 v, c load = 3 nf 2.5 5 r h_tg output resistance, sinking v boot ? v lx = 12v 2.0 2.5 tr drvh transition time c load = 2 nf 16 ns tf drvh transition time c load = 2 nf 11 tpdh drvh propagation delay (notes 1, 2) driving high, c load = 3 nf, v cc = 12 v, v ccp =12 v 15 30 ns ug internal resistor to lx unbiased, boot ? lx = 0 45 k low side driver lg r h_bg output resistance, sourcing v lx = gnd, c load = 3 nf 2.0 3.0 r l_bg output resistance, sinking v lx = v cc 1.0 1.5 tr drvl transition time c load = 3 nf 16 ns tf drvl transition time c load = 3 nf 11 tpdh drvl propagation delay (notes 1, 2) driving high, c load = 3 nf, v ccp = 12 v, v ccp = 12 v 10 20 35 ns lx internal resistor to gnd 45 k thermal shutdown t sd thermal shutdown (note 1) 150 180 c t sdhys thermal shutdown hysteresis (note 1) 50 c 1. guaranteed by design. 2. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram.
ncp81042 http://onsemi.com 7 figure 3. gate timing diagram 1v 1v switching frequency connecting a resistor from rosc/en to an external voltage source v pu will configure the switching frequency. normal range would be 100 khz to 1 mhz. with no resistor connected to the pin, the oscillator frequency is 200 khz. the switching frequency will follow the relationship: f sw 200 khz v pu 1.240 r osc 10 khz a (eq. 1) when r osc = infinity (no resistor connected), f sw = 200 khz; when v pu = ground, the frequency programmed will be higher than 200 khz. pulling r osc /en pin to ground solidly with a less than 10 k resistor will result in the part being disabled. soft ? start soft ? start will begin if vcc, vccp are both above their uvlo thresholds and en pin is set free. ic initially waits a fixed delay time and then ramps the reference in 5.12 ms (1024 clock cycles when r osc open) in closed ? loop regulation. after soft ? start, pgood signal will be released with 3 clock cycles delay. protection active during soft ? start: ? overvoltage protection always enabled; ? undervoltage protection is enabled after reference voltage ramps up to 80% of the final value. during soft ? start, a uvp fault will initiate a complete soft restart. synchronization function synchronize through the sync pin. synchronization function allows different converters to share the same input filter reducing the resulting rms current and reducing the need for total caps to sustain the load. synchronized systems also exhibit higher emi noise immunity and better regulation. the device synchronizes to the falling edge of the sync pin external input signal (eg. high side gate signal, switch node signal, distribution clock signal), and locks the phase of an internal ramp signal correspondingly with a fixed delay time. the external signal has to sit within a 0-40% frequency window above the local frequency configured by the r osc resistor to allow the synchronization function working properly. power good the pgood pin is an open drain connection with no internal pullup resistor. an active high output signals the normal operation of the converter. pgood is pulled low during soft-start cycle, and if there is an overvoltage or undervoltage fault. if the voltage on the vsen pin is within 10% of vref (0.8 v) then the pgood pin will not be pulled low. overvoltage protection (ov) if the voltage on the vsen pin exceeds the overvoltage threshold (1000 mv or 125% vref), the ncp81042 will latch an overvoltage fault. during an overvoltage fault event the ug pin will be pulled low, and the lg pin will stay high until the voltage on the vsen pin goes below 400 mv or 50% v ref , then a soft-bleeding resistor will be connected from switch node to ground to continuously discharge the output voltage softly. to clear the overvoltage fault, toggling vcc or en is needed. undervoltage protection (uv) if the voltage on the fb pin falls below the undervoltage threshold after the softstart cycle completes, the ncp81042 will latch an undervoltage fault. during an undervoltage fault, b oth the ug and lg pins will be pulled low. t oggling vcc power or en will reset the undervoltage protection. preovp protection if the ncp81042 is powered on but not enabled, the vsen pin will be monitored for preovp condition. if the vsen exceeds the preset threshold, the device will force lg pin high to protect the load. the preovp function will be disabled when the device is enabled and the normal ov function will operate instead.
ncp81042 http://onsemi.com 8 vsen vth lg buffer vpu figure 4. preovp circuit vin detection during the soft start after the vsen pin exceeds 80% v ref , uv protection will be enabled; if a uv fault is triggered in the softstart, it will restart ss after a fixed delay. the uv protection is to avoid ic to startup without vin or with insufficient vin voltage. overcurrent protection ncp81042 measures the differential current sensing signal through csp and csn/vo pin. there are two current protection levels: ocp1 and ocp2. if the differential voltage across pin csp and csn/vo is over 20 mv (but below 30 mv) for four consecutive cycles, ocp1 will be tripped. both ug and lg will be forced to low to turn off the high side and low side fets, it is a latched condition; if the differential voltage across pin csp and csn is over 30 mv, ocp2 will be tripped, the ug and lg will be pulled low and latched immediately. toggling vcc power or en will reset the overcurrent protection. the current sensing r/c network should be selected to match the inductor time constant as below, (rcs1 rcs2) c l dcr (notes: the actual rc network time constant may be slightly higher) thus, ocp1 and ocp2 levels can be configured as, ocp1 20 mv dcr rcs1 rcs2 rcs2 ocp2 30 mv dcr rcs1 rcs2 rcs2
ncp81042 http://onsemi.com 9 l dcr rs1 rs2 cs csp csn/vo figure 5. differential current sense network light load operation in the light load condition, ncp81042 will work in a diode emulation mode with bottom gate turning off if the inductor current is below zero. the system therefore works in discontinuous conduction mode (dcm). the zero current detection is done by sensing switch node and automatically adjusted to minimize the low side fet body diode conduction time (right after lg turns off) in diode emulation mode. if the load reduces further, comp signal will be close or below the internal ramp bottom tr iggering minimum on time operation, the system will start skipping pulses, working in a reduced frequency range. ncp81042 has an internal ultrasonic timer to keep the device from working in an audio frequency and below. this timer initiates after high side gate off signal and expires after ~30 s. normally high side gate signal will reset this ultrasonic timer repeatedly before it expires. in a very light load or load release, if there is no high side gate pulses until the timer expires, the low side mosfet(s) will be forced to turn on to discharge the output. through properly compensated network the comp signal will climb up to generate next burst of switching pulses and the converter will regulate the output voltage to its target level. this can last a few cycles or continuously depending on the system load level. in light load operation, if synchronization is enabled, ncp81042 will also check the sync pin input signal cycle by cycle. if the external sync signal is within the synchronization frequency range, the ncp81042 will interleave its switching pulses with it after a proper delay. in this way, the ripple variation during transition between the discontinuous and continuous current mode can be minimized. voltage feedback the ncp81042 allow the output voltage to be adjusted from 0.8 v to 5 v via an external resistor divider network (r1, r2). the controller will regulate the output voltage to maintain the fb pin voltage to 0.8 v reference voltage. the relation between the resistor divider network and the output voltage is as below; r2 r1 0.8 v v out 0.8 v vout vfb r1 r2 figure 6. feedback voltage
ncp81042 http://onsemi.com 10 vin vcc osc/en vout. fb lg (stays low until first pwm pulse except in case of a fault) ug v softstart normal uv monitor ocp/ normal shutdown v vth_disoff (50%v ref ) uvlo_vcc por_vcc v ref = 0.8 v ovp (125%v ref ) softstop ~5ms@200khzz 80% v rer 1024cycle 0.75v 1.24v pre-ovp valid figure 7. start up and shutdown timing diagram
ncp81042 http://onsemi.com 11 vcc > por & vccdr > uvlo _ vccdr boot >uvlo_boot soft start , normal operation ocp, ovp, uvp detection ovp ocp tg off, bg on pgood =0 tg off, bg off vout < vth_disoff vo discharge mode no yes yes oc ov vcc por & vccdr > uvlo _vccdr (16 ? pin ) yes no bg on vsen >ov vth en>vdis_th no figure 8. state diagram
ncp81042 http://onsemi.com 12 package dimensions ??? ??? ??? qfn16 3x3, 0.5p case 485g issue f 16x seating plane l d e 0.10 c a a1 e d2 e2 b 1 4 8 9 16 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. b a 0.10 c top view side view bottom view pin 1 location 0.05 c 0.05 c (a3) c note 4 16x 0.10 c 0.05 c a b note 3 k 16x l1 detail a l alternate terminal constructions ?? a1 a3 l detail b mold cmpd exposed cu alternate constructions detail a detail b *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 2x 0.50 pitch 1.84 3.30 1 dimensions: millimeters 0.58 16x 2x 0.30 16x outline package 2x 2x 0.10 c a b e/2 soldering footprint* dim min nom max millimeters a 0.80 0.90 1.00 a1 0.00 0.03 0.05 a3 0.20 ref b 0.18 0.24 0.30 d 3.00 bsc d2 1.65 1.75 1.85 e 3.00 bsc e2 1.65 1.75 1.85 e 0.50 bsc k 0.18 typ l 0.30 0.40 0.50 l1 0.00 0.08 0.15 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp81042/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of NCP81042MNTXG

	To Download NCP81042MNTXG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .